The present invention relates to a semiconductor memory device, and more particularly, to a circuit for receiving and transferring a clock and command signals of a semiconductor memory device.
A semiconductor memory device serves to store data in a system which includes a plurality of semiconductor devices. When a data processing device, e.g., a central processing unit (CPU), requires data, the semiconductor memory device outputs data corresponding to an address input from the data processing device or stores data received from the data processing device into a memory cell corresponding to the address.
As an operation speed of the system is increased and a semiconductor integrating technology is developed, the semiconductor memory device is required to perform a data access operation at a high speed. For performing the data access operation at a high speed, a synchronous memory device has been developed for performing the data access operation in synchronization with a system clock.
For improving the operation speed of the synchronous memory device, a double data rate (DDR) synchronous memory device has been developed for performing the data access operation in synchronization with both of a rising edge and a falling edge of the system clock.
Since the DDR synchronous memory device should input or output data in synchronization with both of a rising edge and a falling edge of the system clock, the DDR synchronous memory device should process two data within one period of the system clock. That is, the DDR synchronous memory device should output data or store data at every rising edge and every falling edge of the system clock.
Generally, the DDR synchronous memory device receives and transfers the system clock and an inverted system clock to its internal circuit in response to a reference signal. At this time, it is very important to receive the system clock and the inverted system clock at a same duty rate because the DDR synchronous memory device performs its operation in synchronization with the rising edge and the falling edge of the system clock.
FIG. 1 is a schematic diagram illustrating a distortion of a system clock signal input to a semiconductor memory device.
Generally, after fabricating, the semiconductor memory device is arranged at a module and, a plurality of modules form a group. Referring to FIG. 1, first to ninth semiconductor memory devices D1 to D9 form a module, first and second termination resistors R1 and R2 for adjusting input/output impedances of each semiconductor memory device are arranged at one side of the first to ninth semiconductor memory devices D1 to D9, and second to eleventh transmission lines TL1 to TL10 are arranged between the first to ninth semiconductor memory devices D1 to D9.
A data signal input through a first transmission line TL0 is transferred to each semiconductor memory device via the second to eleventh transmission lines TL1 to TL10. A system clock signal and an inverted system clock signal are also transferred to each semiconductor memory device via the second to eleventh transmission lines TL1 to TL10.
At this time, lengths of transmission lines coupled to each semiconductor memory device are different from each other due to differences between positions of the first to ninth semiconductor memory devices D1 to D9. Further, transmission lines for transferring the system clock signal and the inverted system clock signal to each semiconductor memory device are not same.
Accordingly, delay amounts of the system clock signal transferred to each semiconductor memory device are different from each other, and delay amounts of the system clock signal and the inverted system clock signal transferred to each semiconductor memory device are different from each other because impedances of each transmission line does not match with the input impedances of each semiconductor memory device.
As described above, because of a difference between input timings of a system clock signal and an inverted system clock signal input to one semiconductor memory device, a timing margin for receiving the system clock signal in response to a reference signal VREF is different from that for receiving the inverted system clock signal.
For the reference, the reference signal VREF maintains a half voltage level of a section that the system clock signal and the inverted system clock signal are transited. It is desirable that a voltage level of the reference signal VREF is substantially the same as a voltage level of an intersection of the system clock signal and the inverted system clock signal.
However, the voltage level of the reference signal VREF is not same as that of the intersection of the system clock signal and the inverted system clock signal because the delay amount of the system clock signal which is transferred to one semiconductor memory device is different from that of the inverted system clock signal according to a position of the semiconductor memory device.
If a voltage difference of the reference signal VREF and the intersection of the system clock signal and the inverted system clock signal is beyond a permissible range, it is difficult for the semiconductor memory device to receive the system clock signal. Even if the semiconductor memory device receives the system clock signal, an operational timing margin of the semiconductor memory device is reduced.